On design of cache with efficient soft error protection
For critical aerospace applications that experience a high intensity of single event upsets, the cache of a processor has to be protected against soft errors. This poses a challenge for cache design, since implemented redundancy causes timing and performance degradation of a processor. Sound design decisions should be made based on evaluations at every design stage. In this paper we present a platform-oriented design methodology for evaluation of processor vulnerability to soft errors in cache. Results of complex design evaluation for vulnerability, timing and chip area for an FPGA-based design of a typical RISC processor with first level instruction and data caches are presented as well.