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On design of cache with efficient soft error protection

Authors

Mamoutova O.V., Antonov A.P., Filippov A.S.
2017 IEEE 37th International Conference on Electronics and Nanotechnology (ELNANO). Kyiv, Ukraine: IEEE, 2017. P. 57–60. DOI: 10.1109/ELNANO.2017.7939719.

Brief description

For critical aerospace applications that experience a high intensity of single event upsets, the cache of a processor has to be protected against soft errors. This poses a challenge for cache design, since implemented redundancy causes timing and performance degradation of a processor. Sound design decisions should be made based on evaluations at every design stage. In this paper we present a platform-oriented design methodology for evaluation of processor vulnerability to soft errors in cache. Results of complex design evaluation for vulnerability, timing and chip area for an FPGA-based design of a typical RISC processor with first level instruction and data caches are presented as well.

Ключевые слова

Cache memory, performability, performance, reliability, SEU, SoC, soft error, system on chip.

Mamoutova O.V., Antonov A.P., Filippov A.S. On design of cache with efficient soft error protection // 2017 IEEE 37th International Conference on Electronics and Nanotechnology (ELNANO). Kyiv, Ukraine: IEEE, 2017. P. 57–60. DOI: 10.1109/ELNANO.2017.7939719.